What we have done is design an instruction set for a minimal RISC machine
(< 20 instructions). Using a hardware modelling language that runs on the Mac called Verilog we built a simulation of the CPU, memory, a memory controller and a video ram.
We loaded the simulation with hand assembled instructions that implement the startup instructions from the startup of a 'RISCmac' built with this system. It erases the screen to stippled gray, draws a 'happy mac' icon and writes beep data to a 'sound chip'.
Whenever the simulation writes to VRAM or the sound chip the data and it's address are written to a trace file - an application 'riscwindow' reads the trace file and displays the data and plays the sound.
The simulation is written in Verilog an object oriented hardware modelling language, the simulation cpu1.v is a very dumb implementation which doesn't have a cache or write-buffer.
Our (very tounge-in-cheek) theory is that if we can do this in about a day Apple should be shipping a Risc-Mac by the end of the month :-)
Files: system.v system object contains instances of all other objects
(equivalent to a system circuit board)
cpu1.v RISC CPU - includes a description of the instruction set
memory.v DRAM simulation - also the initialization of the memory
with instructions and data
cntrl.v DRAM memory controller and decoder
video.v video and sound trace output
In the directory 'cpu2' there is a rework of the original CPU, this one is pipelined, has data and instruction caches and a write buffer - so it runs much faster - it's not completely debugged but should give you an idea of how it works.
